1. Field
One or more aspects of the inventive concept relate to a semiconductor test system and a method of controlling the same, and more particularly, to a semiconductor test system that includes cores and devices under test (DUTs) that are subject to the IEEE 1149.1 standards and the IEEE 1500 standards.
2. Description of the Related Art
The application specific integrated circuit (ASIC) technology has been developed from the concept of a chipset system to the concept of a system on chip (SoC) based on built-in cores. A SoC integrated circuit includes various functional blocks, e.g., a microprocessor, an interface, a memory array, and/or a digital signal processor (DSP). Such a functional block that has been designed and tested is referred to as a ‘core’.
Even if a plurality of cores are individually tested and are determined as normally operating, the plurality of cores may operate abnormally when they are installed in a SoC. Thus, operations of the plurality of cores should be tested again after they are installed in the SoC.
Various methods, e.g., a built-in self test (BIST), test data compression (TDC), and a multi-site test, have been used for testing DUTs, e.g., a SoC. However, as the BIST and TDC require overheads of relatively large design automatic test equipment (ATE), the BIST and the TDC may be limited to testing SoCs for particular purposes. Further, as the multi-site test performs simultaneous testing of N SoCs, the testing costs may be relatively large, i.e., costs for testing one SoC may be 1/N of the cost of testing N SoCs.